U 0.454260 [VPU:PLATFORM:platform_early_init]: PM_RSTS: 0x1000 0x0 had power on reset PLLC target 500 MHz, CORE0 500 MHz, PER 500 MHz bringing PLLC up at 500MHz xtal_in = 19200000 goal_freq = 250000000 divisor 0xd05555 -> 13+(21845/2^20) waiting for lock VPU now at 500mhz(500), PLLC_CORE0 at 500mhz, PLLC_PER at 500MHz, PLLC at 500mhz bringing PLLA up at 500MHz xtal_in = 19200000 goal_freq = 500000000 divisor 0x1a0aaaa -> 26+(43690/2^20) ctrl: 0x2101a frac: 0x15554 waiting for lock ctrl: 0x2101a frac: 0x15554 ctrl: 0x2101a frac: 0xaaaa bringing PLLH up at 648MHz xtal_in = 19200000 goal_freq = 648000000 divisor 0x21c0000 -> 33+(786432/2^20) ctrl: 0x10000 frac: 0x0 ctrl: 0x1021 frac: 0xc0000 frac set to 0xc0000, wanted 0xc0000 waiting for lock ctrl: 0x21021 frac: 0xc0000 ctrl: 0x21021 frac: 0xc0000 0.526119 [SDRAM:sdram_init]: (0) SD_CS = 0x794200 0.530715 [SDRAM:sdram_init]: stack near 0x8001ffc4 0.535407 [SDRAM:switch_to_cprman_clock]: switching sdram to cprman clock (src=1, div=1), waiting for busy (0x4091) ... 0.545982 [SDRAM:switch_to_cprman_clock]: busy set, switch complete! 0.552143 [SDRAM:reset_phy]: reset_phy: resetting SDRAM PHY ... 0.557931 [SDRAM:reset_phy]: reset_phy: resetting DPHY CTRL ... 0.563609 [SDRAM:sdram_init]: waiting for SDUP (218E42) ... 0.568969 [SDRAM:sdram_init]: SDRAM controller has arrived! (218E42) 0.575128 [SDRAM:calibrate_pvt_early]: cpuid 0x4000140 and dq_slew 2 0.581291 [SDRAM:calibrate_pvt_early]: DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x223 0.588139 [SDRAM:calibrate_pvt_early]: waiting for address PVT calibration ... 0.595166 [SDRAM:calibrate_pvt_early]: waiting for data PVT calibration ... 0.601931 [SDRAM:calibrate_pvt_early]: waiting for SDRAM calibration command ... 0.609144 [SDRAM:sdram_init]: SDRAM Type: Elpida 1GB LPDDR2 (BC=0x58) 0.615398 [SDRAM:reset_with_timing]: SDRAM Addressing Mode: Bank=3 Row=3 Col=3 SB=0xFF 0.623098 [SDRAM:selftest]: Starting self test ... 0.627694 [SDRAM:selftest_at]: Testing region at 0x3FF00000 ... 0.633726 [SDRAM:selftest_at]: Testing region at 0x2FF00000 ... 0.639450 [SDRAM:selftest_at]: Testing region at 0x1FF00000 ... 0.645175 [SDRAM:selftest_at]: Testing region at 0xFF00000 ... 0.650814 [SDRAM:selftest_at]: Testing region at 0x0 ... 0.655932 [SDRAM:selftest]: Self test successful! welcome to lk boot args 0x800110a0 0x0 0x80011d44 0x80011d44 initializing heap calling constructors initializing mp initializing threads initializing timers initializing ports creating bootstrap completion thread top of bootstrap2() arch_init r28: 0x800116e0 sp: 0xc0103598 cpuid: 4000140 ST_CLO: 681563 initializing platform INIT: cpu 0, calling hook 0x80009ada (hvs) at level 0x8fffe, flags 0x1 hvs_init_hook() INIT: cpu 0, calling hook 0x80007694 (vec) at level 0x8ffff, flags 0x1 VEC init image domain starting... bringing up IMAGE domain, reg: 0x7e100108 waiting mem rep de-aserting reset lines usb power on... hvs_initialize() uploading scaling kernel ref: 500000000, target: 108000000, divisor(f): 4.629630, divisor(fixed): 0x4a12 mash not allowed on VEC vec rate: 0.000000, plla: 500000000, pllc: 500000000 setup_pixelvalve, pvnr=2, 720x240 interlaced pv NTSC on at 738206 hvs_configure_channel(1, 720, 480, true) setting up pv interrupt 0.745667 [VPU:PLATFORM:platform_init]: UART break detected A2W_SMPS_A_VOLTS: 0x0 initializing target INIT: cpu 0, calling hook 0x80004186 (vc4_timer) at level 0x90000, flags 0x1 INIT: cpu 0, calling hook 0x80003f98 (grid) at level 0x90001, flags 0x1 legacy layer initializing apps starting app grid starting app shell entering main console loop ]